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s1d15e06 series mf1393-05 rev. 2.1
notice no part of this material may be reproduced or duplicated in any from or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notics. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no repersesnation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ?seiko epson corporation 2003, all rights reserved. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. rev. 2.1
?i sed1575 series rev. 2.1 contents 1. description .................................................................................................................. ................................ 1 2. features ..................................................................................................................... ................................... 1 3. block diagram ................................................................................................................ ............................. 2 4. pin assignment ............................................................................................................... ............................. 3 5. pin description .............................................................................................................. ............................. 7 6. functional description ....................................................................................................... ................. 11 7. command ...................................................................................................................... ................................ 27 8. absolute maximum ratings ..................................................................................................... ............. 50 9. dc characteristics ........................................................................................................... ...................... 51 10. timing characteristics ...................................................................................................... ................... 58 11. mpu interface (reference example) ........................................................................................... .............. 66 12. connection between lcd drivers (reference example) .................................................................. 67 13. lcd panel wiring (reference example) ........................................................................................ ............ 68 14. s1d15e06t00a *** tcp pin layout ........................................................................................................ 69 15. tcp dimensions (reference example) .......................................................................................... ............. 70 16. cautions .................................................................................................................... .................................. 71
s1d15e06 series rev. 2.1 epson 1 2. features direct ram data display by display data ram ?4 gray-scale display (normally white in normal display mode) ram bit data (high order and low order) (1,1) : gray-scale 3, black (1,0) : gray-scale 2 (0,1) : gray-scale 1 (0,0) : gray-scale 0, white ?binary display (normally white display is in normal mode) ram bit data ??: on and black ??: off and white ram capacity 132 160 2 = 42,240 bits liquid crystal drive circuit 132 common outputs and 160 segment outputs high-speed 8-bit mpu interface (directly connectable to the mpus of both 80/68 series) /serial interface possible a variety of command functions area scroll display, partial display, n-line reversal, display data ram address control, contrast control, display on/off, display normal/reverse rotation, display all lighting on/off, liquid crystal drive power supply circuit control, display clock built-in oscillator circuit control lower power mls drive technology built-in high precision voltage regulation function high precision cr oscillator circuit incorporated very low power consumption power supply logic power supply: v dd ?v ss = 1.7 to 3.6 v liquid crystal drive power supply: v 3 ?v ss = 3.4 to 14.0 v (s1d15e06d01 **** ), v 3 ?v ss = 3.4 to 16.0 v (s1d15e06d03 **** ) wide operation temperature range: ?0 to 85 c cmos process shipping form : bare chips, tcp light and radiation proof measures are not taken in designing. 1. description the s1d15e06 series is a single chip mls driver for dot matrix liquid crystal displays which can be directly connected to the microcomputer bus. it accepts the 8- bit parallel or serial display data from the microcomputer to store the data in the on-chip display data ram, and issues liquid crystal drive signals independently of the microcomputer. the s1d15e06 series provides both 4 gray-scale display and binary display. it incorporates a display data ram (132 160 2 bits). in the case of 4 gray-scale display, 2 bits of the on-chip ram respond to one-dot pixels, while in the case of binary display, 1 bit of the on-chip ram respond to one-dot pixels. the s1d15e06 series features 132 common output circuits and 160 segment output circuits. a single chip provides a display of 10 characters by 8 lines with 132 160 dots (16 16 dots) and display of 13 characters by 11 lines by the 12 12 dot-character font. display data ram read/write operations do not require operation clock from outside, thereby ensuring operation with the minimum current consumption. furthermore, it incorporates a lcd-drive power supply characterized by low power consumption and a cr oscillator circuit for display clock; therefore, the display system of a handy and high-performance instrument can be realized by use of the minimum current consumption and minimum chip configuration. series specifications product name bias lcd driving duty (max.) form of shipping chip thickness voltage range s1d15e06d01b000 1/7 3.4v~14.0v 1/132 bare chip 0.400mm s1d15e06d03b000 1/7 3.4v~16.0v 1/132 bare chip 0.400mm s1d15e06d01e000 1/7 3.4v~14.0v 1/132 bare chip 0.625mm S1D15E06D03E000 1/7 3.4v~16.0v 1/132 bare chip 0.625mm s1d15e06t00a00a 1/7 3.4v~14.0v 1/132 tcp
s1d15e06 series 2 epson rev. 2.1 3. block diagram v dd v 1 v c mv 1 mv 2 mv 3 (v ss ) cap4+ cap4 cap1+ cap1 cap2 v out cap2+ cap3+ cap3 cls m/s dof cl f2 f1 ca fr oscillator circuit display timing generator circuit line address i/o buffer cs1 a0 wr (r/w) cs2 d7 (si) d6 (scl) d5 d4 d3 d2 d1 d0 seg0 seg159 com0 com131 com drivers seg drivers display data latch circuit decode circuit display data ram 160 x 132 x 2 column address status command decoder bus holder p/s rd (e) res c86 v ss power supply circuit page address mpu interface v 3 v 2
s1d15e06 series rev. 2.1 epson 3 (0, 0) d15e6d 1b s1d15e06 series die no. 99 98 1 167 344 166 412 345 4. pin assignment 4.1 chip assignment 4.2 alignment mark alignment coordinate 1 (?761.4, 1830.0) m 2 ( 4926.0, ?819.1) m mark size a = 80 m b = 20 m item size unit x y chip size 10.26
s1d15e06 series 4 epson rev. 2.1 101 com64 4958 1575 102 com63 1525 103 com62 1475 104 com61 1425 105 com60 1375 106 com59 1325 107 com58 1275 108 com57 1225 109 com56 1175 110 com55 1125 111 com54 1075 112 com53 1025 113 com52 975 114 com51 925 115 com50 875 116 com49 825 117 com48 775 118 com47 725 119 com46 675 120 com45 625 121 com44 575 122 com43 525 123 com42 475 124 com41 425 125 com40 375 126 com39 325 127 com38 275 128 com37 225 129 com36 175 130 com35 125 131 com34 75 132 com33 25 133 com32 25 134 com31 75 135 com30 125 136 com29 175 137 com28 225 138 com27 275 139 com26 325 140 com25 375 141 com24 425 142 com23 475 143 com22 525 144 com21 575 145 com20 625 146 com19 675 147 com18 725 148 com17 775 149 com16 825 150 com15 875 51 d4 170 1830 52 d5 262 53 d6, scl 354 54 d7, si 446 55 v ss 538 56 v ss 630 57 v ss 722 58 v dd 814 59 v dd 906 60 v dd 998 61 v out 1090 62 v out 1182 63 cap1+ 1274 64 cap1+ 1366 65 cap1 1458 66 cap1 1550 67 cap2 1642 68 cap2 1734 69 cap2+ 1826 70 cap2+ 1918 71 cap3+ 2010 72 cap3+ 2102 73 cap3 2194 74 cap3 2286 75 cap4 2378 76 cap4 2470 77 cap4+ 2562 78 cap4+ 2654 79 v 3 2746 80 v 3 2838 81 v 2 2930 82 v 2 3022 83 v 1 3114 84 v 1 3206 85 v c 3298 86 v c 3390 87 mv 1 3482 88 mv 1 3574 89 mv 2 3666 90 mv 2 3758 91 mv 3 3850 92 mv 3 3942 93 cpp+ 4034 94 cpp 4126 95 cpm+ 4218 96 cpm 4310 97 nc 4402 98 nc 4494 99 nc 4958 1675 100 com65 1625 1 nc 4494 1830 2 nc 4402 3 test0 4310 4 test1 4218 5 test2 4126 6 test3 4034 7 test4 3942 8 test5 3850 9v ss 3742 10 test6 3634 11 test7 3542 12 test8 3450 13 test9 3358 14 test10 3266 15 test11 3174 16 test12 3082 17 test13 2990 18 test14 2898 19 test15 2806 20 test16 2714 21 test17 2622 22 test18 2530 23 v ss 2422 24 fr 2314 25 cl 2222 26 dof 2130 27 f1 2038 28 f2 1946 29 ca 1854 30 v ss 1762 31 test 1670 32 cs1 1578 33 res 1486 34 a0 1394 35 wr, r/w 1302 36 rd, e 1210 37 cs2 1118 38 v dd 1026 39 m/s 934 40 v ss 842 41 cls 750 42 v dd 658 43 c86 566 44 v ss 474 45 p/s 382 46 v dd 290 47 d0 198 48 d1 106 49 d2 14 50 d3 78 pad pin xy no. name pad pin xy no. name pad pin xy no. name unit: 4.3 pad center coordinates
s1d15e06 series rev. 2.1 epson 5 201 seg25 2725 1818 202 seg26 2675 203 seg27 2625 204 seg28 2575 205 seg29 2525 206 seg30 2475 207 seg31 2425 208 seg32 2375 209 seg33 2325 210 seg34 2275 211 seg35 2225 212 seg36 2175 213 seg37 2125 214 seg38 2075 215 seg39 2025 216 seg40 1975 217 seg41 1925 218 seg42 1875 219 seg43 1825 220 seg44 1775 221 seg45 1725 222 seg46 1675 223 seg47 1625 224 seg48 1575 225 seg49 1525 226 seg50 1475 227 seg51 1425 228 seg52 1375 229 seg53 1325 230 seg54 1275 231 seg55 1225 232 seg56 1175 233 seg57 1125 234 seg58 1075 235 seg59 1025 236 seg60 975 237 seg61 925 238 seg62 875 239 seg63 825 240 seg64 775 241 seg65 725 242 seg66 675 243 seg67 625 244 seg68 575 245 seg69 525 246 seg70 475 247 seg71 425 248 seg72 375 249 seg73 325 250 seg74 275 251 seg75 225 1818 252 seg76 175 253 seg77 125 254 seg78 75 255 seg79 25 256 seg80 25 257 seg81 75 258 seg82 125 259 seg83 175 260 seg84 225 261 seg85 275 262 seg86 325 263 seg87 375 264 seg88 425 265 seg89 475 266 seg90 525 267 seg91 575 268 seg92 625 269 seg93 675 270 seg94 725 271 seg95 775 272 seg96 825 273 seg97 875 274 seg98 925 275 seg99 975 276 seg100 1025 277 seg101 1075 278 seg102 1125 279 seg103 1175 280 seg104 1225 281 seg105 1275 282 seg106 1325 283 seg107 1375 284 seg108 1425 285 seg109 1475 286 seg110 1525 287 seg111 1575 288 seg112 1625 289 seg113 1675 290 seg114 1725 291 seg115 1775 292 seg116 1825 293 seg117 1875 294 seg118 1925 295 seg119 1975 296 seg120 2025 297 seg121 2075 298 seg122 2125 299 seg123 2175 300 seg124 2225 151 com14 4958 925 152 com13 975 153 com12 1025 154 com11 1075 155 com10 1125 156 com9 1175 157 com8 1225 158 com7 1275 159 com6 1325 160 com5 1375 161 com4 1425 162 com3 1475 163 com2 1525 164 com1 1575 165 com0 1625 166 nc 1675 167 nc 4704 1846 168 nc 4621 169 nc 4539 170 nc 4456 171 nc 4374 172 nc 4291 173 nc 4209 174 nc 4126 175 nc 4044 176 seg0 3975 1818 177 seg1 3925 178 seg2 3875 179 seg3 3825 180 seg4 3775 181 seg5 3725 182 seg6 3675 183 seg7 3625 184 seg8 3575 185 seg9 3525 186 seg10 3475 187 seg11 3425 188 seg12 3375 189 seg13 3325 190 seg14 3275 191 seg15 3225 192 seg16 3175 193 seg17 3125 194 seg18 3075 195 seg19 3025 196 seg20 2975 197 seg21 2925 198 seg22 2875 199 seg23 2825 200 seg24 2775 pad pin xy no. name pad pin xy no. name pad pin xy no. name unit:
s1d15e06 series 6 epson rev. 2.1 301 seg125 2275 1818 302 seg126 2325 303 seg127 2375 304 seg128 2425 305 seg129 2475 306 seg130 2525 307 seg131 2575 308 seg132 2625 309 seg133 2675 310 seg134 2725 311 seg135 2775 312 seg136 2825 313 seg137 2875 314 seg138 2925 315 seg139 2975 316 seg140 3025 317 seg141 3075 318 seg142 3125 319 seg143 3175 320 seg144 3225 321 seg145 3275 322 seg146 3325 323 seg147 3375 324 seg148 3425 325 seg149 3475 326 seg150 3525 327 seg151 3575 328 seg152 3625 329 seg153 3675 330 seg154 3725 331 seg155 3775 332 seg156 3825 333 seg157 3875 334 seg158 3925 335 seg159 3975 336 nc 4044 1846 337 nc 4126 338 nc 4209 339 nc 4291 340 nc 4374 341 nc 4456 342 nc 4539 343 nc 4621 344 nc 4704 345 nc 4958 1675 346 com66 1625 347 com67 1575 348 com68 1525 349 com69 1475 350 com70 1425 351 com71 4958 1375 352 com72 1325 353 com73 1275 354 com74 1225 355 com75 1175 356 com76 1125 357 com77 1075 358 com78 1025 359 com79 975 360 com80 925 361 com81 875 362 com82 825 363 com83 775 364 com84 725 365 com85 675 366 com86 625 367 com87 575 368 com88 525 369 com89 475 370 com90 425 371 com91 375 372 com92 325 373 com93 275 374 com94 225 375 com95 175 376 com96 125 377 com97 75 378 com98 25 379 com99 25 380 com100 75 381 com101 125 382 com102 175 383 com103 225 384 com104 275 385 com105 325 386 com106 375 387 com107 425 388 com108 475 389 com109 525 390 com110 575 391 com111 625 392 com112 675 393 com113 725 394 com114 775 395 com115 825 396 com116 875 397 com117 925 398 com118 975 399 com119 1025 400 com120 1075 401 com121 4958 1125 402 com122 1175 403 com123 1225 404 com124 1275 405 com125 1325 406 com126 1375 407 com127 1425 408 com128 1475 409 com129 1525 410 com130 1575 411 com131 1625 412 nc 1675 pad pin xy no. name pad pin xy no. name pad pin xy no. name unit:
s1d15e06 series rev. 2.1 epson 7 5. pin description 5.1 power pin v 2 11/14 v 3 v 1 9/14 v 3 v c 7/14 v 3 mv 1 5/14 v 3 mv 2 3/14 v 3 pin name i/o description number of pins v dd power connect to system mpu power supply pin v cc .6 supply v ss power connect to the system gnd. 8 supply mv 3 is short circuited with m v3 inside the ic chip. v 3 , v 2 , v 1 , power a liquid crystal drive multi-level power supply. the voltages 14 v c , mv 1 , supply determined by the liquid crystal cell are impedance-converted by (2 each) mv 2 , mv 3 , resistive divider and operational amplifier for application. (=v ss ) the following order must be maintained: v 3 5.2 lcd power supply circuit pin pin name i/o description number of pins cap1+ o pin connected to the positive side of the step-up capacitor. 2 connect the capacitor between this pin and cap1 pin. cap1 o pin connected to the negative side of the step-up capacitor. 2 connect the capacitor between this pin and cap1+ pin. cap2+ o pin connected to the positive side of the step-up capacitor. 2 connect the capacitor between this pin and cap2 pin. cap2 o pin connected to the negative side of the step-up capacitor. 2 connect the capacitor between this pin and cap2+ pin. v out o output pin for step-up. 2 connect the capacitor between this pin and v dd . cap3+ o pin connected to the positive side of the step-up capacitor. 2 connect the capacitor between this pin and cap3 pin. cap3 o pin connected to the negative side of the step-up capacitor. 2 connect the capacitor between this pin and cap3+ pin. cap4+ o pin connected to the positive side of the step-up capacitor. 2 connect the capacitor between this pin and cap4 pin. cap4 o pin connected to the negative side of the step-up capacitor. 2 connect the capacitor between this pin and cap4+ pin. cpp+ o keep it open. 1 cpp o keep it open. 1 cpm+ o keep it open. 1 cpm o keep it open. 1
s1d15e06 series 8 epson rev. 2.1 p/s data/command data read/write serial clock high a0 d0 to d7 rd, wr low a0 si (d7) write only scl (d6) 5.3 system bus connection pin pin name i/o description number of pins d7 to d0 i/o connects to the 8-bit or 16-bit mpu data bus via the 8-bit 8 bi-directional data bus. (si) when the serial interface is selected (p/s = low), d7 serves as the (scl) serial data input (si) and d6 serves as the serial clock input (scl), in this case, d0 through d5 go to a high impedance state. when the chip select is inactive, d0 through d7 go to a high impedance state. a0 i normally, the least significant bit mpu address bus is connected 1 to distinguish between data and command. a0 = high : indicates that d0 to d7 are display data or command parameters. a0 = low : indicates that d0 to d7 are control commands. res i when the res is low, initialization is achieved. 1 resetting operation is done on the level of the res signal. cs1 i a chip select signal. when cs1 = low and cs2 = high, signals 2 cs2 are active, and data/command input/output are enabled. rd i when the 80 series mpu is connected. 1 (e) a pin for connection of the rd signal of the 80 series mpu. when this signal is low, the data bus of the s1d15e06 series is in the output state. when the 68 series mpu is connected. serves as a 68 series mpu enable clock input pin. wr i when the 80 series mpu is connected. 1 (r/w) a pin for connection of the wr signal of the 80 series mpu. signals on the data bus are latched at the leading edge of the wr signal. serves as a read/write control signal input pin when the 68 series mpu is connected. r/w = high : read r/w = low : write c86 i a mpu interface switching pin. 1 c86 = high : 68 series mpu interface c86 = low : 80 series mpu interface p/s i parallel data input/serial data input select pin 1 p/s = high : parallel data input p/s = low : serial data input the following table shows the summary: when p/s = low, d0 to d5 are high impedance. d0 to d5 can be high, low or open. rd(e) and wr(r/w) are locked to high or low. the serial data input does not allow the ram display data to be read.
s1d15e06 series rev. 2.1 epson 9 pin name i/o description number of pins cls i a pin used to select enable/disable state of the built-in oscillator 1 circuit for display clock. cls = high : built-in oscillator circuit enabled cls = low : built-in oscillator circuit disabled (external input) when cls is low, display clock is input from the cl pin. when the s1d15e06 series is used in the master/slave mode, each cls pins must be set to the same level. m/s i a pin used to select the master/slave operation for s1d15e06 series. 1 liquid crystal display system is synchronized when the master operation outputs the timing signal required for liquid crystal display, while the slave operation inputs the timing signal required for liquid crystal display. m/s = high : master operation m/s = low : slave operation the following table shows the relation in conformance to the m/s and cls: the slave power supply circuit can also operate, but do not use it. cl i/o display clock input/output pin. 1 the following table shows the relation in conformance to the m/s and cls state: when you want to use the s1d15e06 series in the master/slave mode, connect each cl pin. fr i/o a liquid crystal alternating current input/output pin. 1 m/s = high : output m/s = low : input when you want to use the s1d15e06 series in the master/slave mode, connect each fr pin. f1, f2, i/o a liquid crystal sync signal input/output pin. 3 ca m/s = high : output (1 each) m/s = low : input when you want to use the s1d15e06 series in the master/slave mode, connect each f1, f2 and ca pins. dof i/o a liquid crystal blanking control pin. 1 m/s = high : output m/s = low : input when you want to use the s1d15e06 series in the master/slave mode, connect each dof pin. m/s cls cl high high output low input low high input low input m/s cls oscillation power cl fr, dof, circuit circuit f1, f2, ca high high enabled enabled output output low disabled enabled input output low high disabled disabled input input low disabled disabled input input display clock master slave built-in oscillator circuit used high high external input low low
s1d15e06 series 10 epson rev. 2.1 5.4 liquid crystal drive pin 5.5 test pins pin name i/o description number of pins seg0 to o liquid crystal segment drive output pins. one of the v 2 , v 1 , v c , 160 seg159 mv 1 , and mv 2 levels is selected by a combination of the display ram content and fr/f1/f2 signals. com0 to o liquid crystal common drive output pins. one of the v 3 , v c , 132 com131 mv 3 (v ss ) levels is selected by a combination of the scan data and fr/f1/f2 signals. pin name i/o description number of pins test, i ic chip test pins. lock them to low. 5 test2 to 5 test0, 1, i/o ic chip test pins. open them and make sure that the capacity is not 15 6 to 18 consumed by wiring, etc.
s1d15e06 series rev. 2.1 epson 11 6. functional description 6.1 mpu interface 6.1.1 selection of interface type s1d15e06 series allows data to be sent via the 8-bit bi-directional data buses (d7 to d0) or serial data input (si). by setting the polarity of the p/s pin to high or low, you can select either 8-bit parallel data input or serial data input, as shown in table 6.1. table 6.1 6.1.2 parallel interface when the parallel interface is selected (p/s = high), direction connection to the mpu bus of either 80 series mpu or 68 series mpu is performed by setting the 86 pin to either high or low, as shown in table 6.2. table 6.2 the data bus signals are identified by a combination of a0, rd (e), and wr (r/w) signals as shown in table 6.3. table 6.3 6.1.3 serial interface when the serial interface is selected (p/s =low), the chip is active (cs1 = low, cs2 = high), and reception of serial data input (si) and serial clock input (scl) is enabled. serial interface comprises a 8-bit shift register and 3-bit counter. the serial data are latched by the rising edge of serial clock signals in the order of d7, d6, .... and d0 starting from the serial data input pin. on the rising edge of 8th serial clock signal, they are converted into 8-bit parallel data to be processed. whether serial data input is a display data or command is identified by a0 input. a0 = high indicates display data, while a0 = low shows command data. the a0 input is read and identified at every 8 n-th rising edge of the serial clock after the chip has turned active. fig. 6.1 shows the serial interface signal chart. p/s cs1 cs2 a0 rd wr d7 to d0 high : 68 series mpu bus cs1 cs2 a0 e r/w d7 to d0 low : 80 series mpu bus cs1 cs2 a0 rd wr d7 to d0 common 68 series 80 series a0 r/w rd wr function 1101display data read, status read 1010 display data write, command parameter write 0110comm and write p/s cs1 cs2 a0 rd wr c86 d7 d6 d5 to d0 high : parallel input cs1 cs2 a0 rd wr c86 d7 d6 d5 to d0 low : serial input cs1 cs2 a0 si scl (hz) : fixed to high or low hz: high impedance state
s1d15e06 series 12 epson rev. 2.1 6.1.4 chip selection the s1d15e06 series has two chip select pins; cs1 and cs2. mpu interface or serial interface is enabled only when cs1 = low and cs2 = high. when the chip select pin is inactive, d0 to d5 are in the state of high impedance, while a0, rd and wr inputs are disabled. when serial interface is selected, the shift register and counter are reset. 6.1.5 access to display data ram and internal register access to s1d15e06 series viewed from the mpu side is enabled only if the cycle time requirements are kept. this does not required waiting time; hence, high-speed data transfer is allowed. furthermore, at the time of data transfer with the mpu, s1d15e06 series provides a kind of inter-lsi pipe line processing via the bus holder accompanying the internal data bus. for example, when data is written to the display data ram by the mpu, the data is once held by the bus holder. it is written to the display data ram before the next data write cycle comes. on the other hand, when the mpu reads the content of the display data ram, it is read in the first data read cycle (dummy), and the data is held in the bus holder. then it is read onto on the system bus from the bus holder in the next data read cycle. restrictions are imposed on the display data ram read sequence. when the address has been set, specified address data is not output to the read command immediately after that. the specified address data is output in the second data reading. this must be carefully noted. therefore, one dummy read operation is mandatory subsequent to address setting or write cycle. fig. 6.2 illustrates this relationship. fig. 6.1 * when the chip is inactive, the counter is reset to the initials state. * reading is not performed in the case of serial interface. * for the scl signal, a sufficient care must be taken against terminal reflection of the wiring and external noise. recommend to use an actual equipment to verify the operation. cs2 si scl a0 cs1 d7 1234567891011121314 d6 d5 d4 d3 d2 d7 d6 d5 d4 d3 d2 d1 d0
s1d15e06 series rev. 2.1 epson 13 write white latch n n+1 n+2 n n+1 n+2 wr mpu internal timing data command bus holder write signal a0 read fig. 6.2 read dumy n n+1 n+2 increment n+1 preset n read command code n n+1 n+2 data read data read dummy read wr rd data read signal column address bus holder mpu internal timing a0 command 6.2 display data ram 6.2.1 display data ram this is a ram to store the display dot data, and comprises 132 160 2 bits. access to the desired bit is enabled by specifying the page address and column address. when the 4 gray-scale is selected by the display mode command, display data input for gray-scale display are processed as a two-bit pair. combination is as follows: (msb, lsb) = (d1,d0), (d3,d2), (ds,d4), (d7,d6) when the ram bit data is gray-scale 1 and 2, gray-scale display is realized according to the parameter of the gray-scale pattern set command. ram bit data (high order and low order) (1,1) : gray-scale 3 bl ack (when display is in normal mode) (1,0) : gray-scale 2 (0,1) : gray-scale 1 (0,0) : gray-scale 0 wh ite (when display is in normal mode) when binary display is selected by the display mode command, the ram 1 bit built in the one-dot pixel responds to it. when the ram bit data is ?? the display is black. if it is ?? the display is given in white. ram bit data ??: light on bl ack (when display is in normal mode) ??: light off wh ite (when display is in normal mode)
s1d15e06 series 14 epson rev. 2.1 fig. 6.3 4 gray-scale (d1,d0) (d3,d2) (d5,d4) (d7,d6) (0,0) (1,1) (0,0) (0,0) (1,1) (0,0) (1,0) (0,0) (1,1) (0,0) (0,1) (0,0) (0,0) (0,0) (0,0) (0,0) display data ram com0 com1 com2 com3 lcd display data d7 to d0 from the mpu correspond to lcd common direction, as shown in fig. 6.3 and 6.4. therefore, less restrictions when multi-chip usage. furthermore, read/write operations from the mpu to the ram are carried out via the input/output buffer. the read operation from display data ram is designed as an independent operation. accordingly, even if the mpu accesses the ram asynchronously during lcd display, no adverse effect is given to display. fig. 6.4 binary 6.2.2 gray-scale display when the 4 gray-scale is selected by the display mode command, gray-scale is represented by the frm control carried out according to the gray-scale data written in the display data ram. of the 4 gray-scale, 2 gray-scale of halftones (gray- scale 2 and 1) has its level of contrast specified by the gray-scale set command. gray-scale can be selected from 6 levels of contrast. 6.2.3 page address circuit/column address circuit the address of the display data ram to be accessed is specified by the page address set command and column address set command, as shown in fig. 6.5 and fig. 6.6. for address incremental direction, either the column direction or page direction can be selected by the address direction command. whichever direction is chosen, increment is carried out by positive one (+1) after write or read operation. when the column direction is selected for address increment, the column address is increased by +1 for every write or read operation. after the column address has accessed up to 9fh, the page address is incremented by +1 and the column address shifts to 0h. when the page direction is selected for address increment, the page address is increased with the column address locked in position. when the page address has accessed up to 32h, the column address is incremented by +1, and the page address goes to 0h. whichever direction is selected for address increment, the page address goes back to 0h and the column address to 0h after access up to the column address 9fh of page address 32h. as shown in fig. 6.4, relationship between the display data ram column address and segment output can be reversed by the column address set direction command. this will reduce restrictions on ic layout during lcd module assembling. d0 d1 d2 d3 d4 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 display data ram com0 com1 com2 com3 com4 lcd
s1d15e06 series rev. 2.1 epson 15 6.2.4 line address circuit the line address circuit specifies the line address corresponding to com output when the contents of the display data ram is displayed, as shown in fig. 6.5 and 6.6. normally, the top line of the display (com0 output in the case of normal rotation of the common output status and com131 output in the case of reverse rotation) is specified by the display start line address set command. the display area starts from the specified display start line address to cover the area corresponding to the lines specified by the duty set command in the direction where the line address increments. if the display start line address set command is used for table 6.4 seg output seg0 seg159 adc 0 0(h) 1 9f(h) dynamic modification of the line address, screen scroll and page change are enabled. 6.2.5 area scroll the display area can be divided into the display area fixed in the com direction and scrollable area by the area scroll command. the scroll area is set by a scroll mode, scroll start line address (as), scroll end address (ae), and scroll display line count (al) as parameters for the area scroll command. display start line address (dl) in the scroll area can be specified by the display start line address set command. 6.2.5.1 mode 0 (full screen scroll) this mode releases the area scroll. parameters as, ae and al are disabled, 6.2.5.2 mode 1 (upper scroll ) reading starts from the line address dl to read al lines as a scroll area. if the line address ae is read in the middle of reading the scroll area, the line address to be read next will be 00h. when all the al lines have been read, the address to be read next will be ae + 1. when reading is completed up to the final line address, the control goes back to the line address dl, and parameter as is disabled. dl can be specified in the range from 00h to ae. scrollable scrollable fixed area fixed area scrollable fixed area fixed area scrollable mode 0 mode 1 mode 2 mode 3 upper fixed area number of line : as scroll area number of line : al lower fixed area number of line 00h dl ae+1 final line address as-1 scroll mode
s1d15e06 series 16 epson rev. 2.1 6.2.5.3 mode 2 (lower scroll) reading starts from line address 00h to reach the line address as-1 in the continuous reading mode. upon completion of reading of line address as-1, the line address moves to the dl to read the area corresponding to al lines from the line address dl as a scroll area. if the final line address is read in the middle of reading the scroll area, the line address to be read next will be as. when all al lines have been read, the control goes back to the line address 00h, and parameter ae is disabled. dl can be specified in the range from as to the final line address. 6.2.5.4 mode 3 (center scroll) reading starts from line address 00h to reach the line address as-1 in the continuous reading mode. upon completion of reading of line address as-1, the line address moves to the dl to read the area corresponding to al lines from the line address dl as a scroll area. if the final line address is read in the middle of reading the scroll area, the line address to be read next will be as. when all al lines have been read, the line address will be ae+1. when up to the final line address has been read, the control goes back to the line address 00h, dl can be specified in the range from as to ae. 6.2.6 display data latch circuit the display data latch circuit is a latch to temporarily latch the display data output from then display data ram to the liquid crystal drive circuit. display normal/ reverse, display on/off, and display all lighting on/ off commands control the data in this latch, without the data in the display data ram being controlled. 6.2.7 partial display partial display of the screen is provided by the partial display on/off command. the partial area (display start line, number of display lines) are set by the partial display set command. the display start line of the parameter shows the line assigned in the com direction of the liquid crystal screen. it is different from the line address given in fig. 6.5 and 6.6. example: when the point is set at 1 (com4 to 7) by the duty reset command, the display line is assigned as shown below. if the display start line 4 and display line count 3 are specified by the partial display set command, the display area is com8 to com10. display line lcd panel 0 1 2 3 4 5 6 7 8 9 10 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14
s1d15e06 series rev. 2.1 epson 17 fig. 6.5 4 gray-scale page address data d1,d0 d3,d2 d5,d4 d7,d6 d1,d0 d3,d2 d5,d4 d7,d6 d1,d0 d3,d2 d5,d4 d7,d6 d1,d0 d3,d2 d5,d4 d7,d6 d1,d0 d3,d2 d5,d4 d7,d6 d1,d0 d3,d2 d5,d4 d7,d6 d1,d0 d3,d2 d5,d4 d7,d6 d1,d0 d3,d2 d5,d4 d7,d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 start line address com output common output state: normal rotation com0 com1 com2 com3 com4 com4 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com124 com125 com126 com127 com128 com129 com130 com131 page 0 page 1 page 2 page 3 page 4 page 5 page 31 page 32 seg0 seg1 seg2 seg3 seg4 seg5 seg154 seg155 seg156 seg157 seg158 seg159 lcd out 9f 9e 9d 9c 9b 9a 05 04 03 02 01 00 1 d0 00 01 02 03 04 05 9a 9b 9c 9d 9e 9f 0 d0 adc column address 132 lines 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 7ch 7dh 7eh 7fh 80h 81h 82h 83h 4 gray-scale display when the display start line is set to 11h
s1d15e06 series 18 epson rev. 2.1 fig. 6.6 binary display d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com121 com122 com123 com124 com125 com126 com127 com128 com129 com130 com131 0 0 0 0 page 0 0 0 0 1 page 1 0 0 1 0 page 2 0 0 1 1 page 3 0 1 0 0 page 4 0 1 0 1 page 5 1 1 1 1 page 15 0 0 0 0 page 16 page 17 page 18 page 31 page 32 page address d3 d2 d1 d0 data line address com output common output state: normal mode binary display when the display start line is set to 0ch start 00 01 00 10 11 11 00 00 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 9f 9e 9d 9c 9b 9a 99 98 00 01 02 03 04 05 06 07 seg152 seg153 seg154 seg155 seg156 seg157 seg158 seg159 07 06 05 04 03 02 01 00 98 99 9a 9b 9c 9d 9e 9f lcd out adc column address 1 d0 0 d0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 79h 7ah 7bh 7ch 7dh 7eh 7fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 4fh 50h f9h fah fbh fch fdh feh ffh 100h 101h 102h 103h 104h 105h 106h 107h d5 d4 00 00 00 00 00 00 00 01 01 01 01 10 ......... ......... ......... ......... ......... ......... ......... 132 lines
s1d15e06 series rev. 2.1 epson 19 operating mode cl fr, ca, f1, f2, dof master (m/s = high) built-in oscillator circuit enabled (cls = high) output output built-in oscillator circuit disabled (cls = low) input output slave (m/s = low) built-in oscillator circuit enabled (cls = high) input input built-in oscillator circuit disabled (cls = low) input input table 6.5 6.3 oscillator circuit a display clock is generated by the cr oscillator. the oscillator circuit is enabled only when m/s = high and cls = high. oscillation starts after input of the built- in oscillator circuit on command input. when cls = low, oscillation stops, and display clock is input from the cl pin. 6.4 display timing generation circuit timing signals are generated from the display clock to the line address circuit and display data latch circuit. synchronized with display clock, display data is latched in display data latch circuit, and is output to the segment drive output pin. reading of the display data into the lcd drive circuit is completely independent of access from the mpu to the display data ram. accordingly, asynchronous access to the display data ram during lcd display does not give any adverse effect; like as flicker. furthermore, the display clock generates internal common timing, liquid crystal alternating signal(fr), field start signal (ca) and drive pattern signal (fl and f2). the fr normally generates 2-frame alternating drive system drive waveform to the liquid crystal drive circuit. the n-line reverse alternating drive waveform is generated for each 4 (a+1) line by setting data on the n-line reverse drive register. when there is a display quality problem including crosstalk,the problem may be solved using the n-line reverse alternating drive. execute liquid crystal display to determine the number of lines ??for alternation. when you want to use the s1d15e06 series in multi- chip configuration, supply display timing signal (fr, ca, f1, f2, cl, dof) to the slave side from the master side. table 6.5 shows the statuses of fr, ca, f1, f2, cl, dof. 6.5 liquid crystal drive circuit 6.5.1 seg drivers this is a seg output circuit. it selects the five values of v 2 , v 1 , v c , mv 1 and mv 2 using the driver control signal determined by the decoder, and output them. 6.5.2 com drivers this is a com output circuit. it selects three values of v 3 , v c and mv 3 (v ss ) using the driver control signal determined by the decoder, and output them. s1d15e06 series allows the com output scanning direction to be set by the common output status select command. (see table 6.6). this will reduce restrictions on ic layout during lcd module assembling. status direction of com scanning normal com 0 table 6.6
s1d15e06 series 20 epson rev. 2.1 circuits used d4 d3 d2 d1 d0 step-up v c regulator lcdv eternal input circuit circuit circuit power supply 1 1 1 1 double step-up 10111 1 1 1 v out = v dd 01111 1 1 1 2 0 1 1 v out lcdv circuit only 3 0 0 1 v c 4 0 0 0 v 3 , v 2 , v 1 , v c , only (s1d15e06d00b * )mv 1 , mv 2 * any combinations other than the above are not available. *100ms or more should be kept from v c regulator circuit on to lcdv circuit on. table 6.8 reference combination table 6.7 control by 5-bit data of the control set command item state triple double single ? ? d4 step-cut circuit scaling factor select bit 1 110 d3 step-cut circuit scaling factor select bit 2 101 d2 step-cut circuit control bit on off d1 voltage regulator circuit (v c regulator circuit) control bit on off d0 lcd driving potential generating circuit (lcdv circuit) control bit on off 6.6 power supply circuit this is a power supply circuit to generate voltage required for liquid crystal drive, and is characterized by a low power consumption. it consists of a step-up circuit, voltage regulating circuit and liquid crystal drive voltage generating circuit, and is enabled only during master operation. the power supply circuit uses the power control set command to provide an on/off control of step-up circuit, voltage regulating circuit and liquid crystal drive potential generating circuit. this allows a combined use of the external power supply and part of built-in power supply functions. table 6.7 shows functions controlled by the 5-bit data of the control set command, and table 6.8 shows reference combinations. the power supply circuit is enabled only during master operation.
s1d15e06 series rev. 2.1 epson 21 s1d15e06 s1d15e06 v dd v out cap1+ cap1 c1 c1 c1 c1 c1 + + v dd v out cap1+ cap1 cap2 cap2+ cap2+ cap2 + + + v dd = 2v v ss = 0v v out = 3 x v dd = 6v v dd = 3v v ss = 0v v out = 2 x v dd = 6v s1d15e06 v dd v out cap1+ cap1 open cap2+ cap2 v ss = 0v v out = v dd = 3.6v open open open open 6.6.1 step-up circuit v dd -v ss potential can be triple and double step-up by the step-up circuit built in the s1d15e06 series. the status of v out = v dd can be selected by stopping the operation of the triple and double step-up circuit using the command 1 when used by switching between the triple, double step-up and v out = v dd using a command: capacitors c1 are connected between cap1+ <-> cap1, between cap2+ <-> cap2 and between v dd <-> v out for use. 2 when used by switching between the double step-up and v out = v dd using a command: capacitors c1 are connected between cap1+ <-> cap1 and between v dd <-> v out for use. 3 only v out = v dd is used. v dd pin and v out pin are connected for use. 2 double step-up or v out = v dd 1 triple, double step-up or v out = v dd 3 v out = v dd (without step-up) triple step-up potential relationship double step-up potential relationship v out = v dd potential relationship fig. 6.7 * set the v dd voltage range so that the v out pin voltage does not exceed the absolute maximum rating. fig.6.7 shows the potential relationship for boosting.
s1d15e06 series 22 epson rev. 2.1 6.6.2 voltage regulating circuit v out generated from the step-up circuit or v out input from the outside produces liquid crystal drive voltage v c via the voltage regulating circuit. the voltage regulating circuit is controlled by liquid crystal drive voltage change command and electronic volume. the s1d15e06 series has a high precision constant voltage source, and incorporates 4-step liquid crystal drive voltage change command and 128-step electronic volume functions. this makes it possible to provide a high precision liquid crystal drive voltage regulation only by the command without adding any external parts. the variable range of the v c voltage is from about 1.6 to 7.0 [v]. when the internal step-up is used, or v out is input for use, the v out potential should be, in principle, the voltage 20% or more higher than the maximum voltage of the v c to be used, giving consideration to temperature characteristics. example: when v c output is 7 [v], v out 8.4 [v] (three times 2.8 [v], etc.) when v c output is 4 [v], v out 4.8 [v] (two times 2.4 [v], three times 1.8 [v]) ?electronic volume of table 6.9 indicates an electronic volume command value. it takes one of 128 states when the data is set in the 7-bit electronic volume register. table 6.9 shows the value of by setting the data in the electronic volume register. table 6.9 d6 d5 d4 d3 d2 d1 d0 voltage v c 0 0 0 0 0 0 0 0 small 00000011 ?liquid crystal drive voltage selection the liquid drive voltage range can be selected from 3 states by the liquid crystal drive voltage select command using the two-bit crystal drive voltage select command register. table 6.10 d1 d0 v c voltage output range 0 0 1.77v to 3.50v 1 0 2.53v to 5.00v 1 1 3.54v to 7.00v
s1d15e06 series rev. 2.1 epson 23 7 6 5 4 3 2 1 0 v c value of electronic volume equation a-1 represents v c logical values. for the output voltage of v c , a manufacturing dispersion of up to 3% should be taken into account. equation a-1 unit [v] electronic lcd voltage selection v r d1 d0 d1 d0 d1 d0 32) 3.42 + 0.0223 32) 4.78 + 0.0313 32) 64 to 95 2.89 + 0.0117 64) 4.12 + 0.0167 64) 5.77 + 0.0234 64) 96 to 127 3.26 + 0.0078 96) 4.65 + 0.0112 96) 6.52 + 0.0156 96)
s1d15e06 series 24 epson rev. 2.1 an example of circuit around the power supply circuit 1 use of all built-in power supplies when used by switching between the triple, double boosting and v out = v dd : (12 c?) when used by switching between the double boosting and v out = v dd : (11 c?) + + + + + cap1+ cap1 cap2 cap2+ v out v dd c1 + + + c1 cpp+ cpp cpm+ cpm v 3 v 2 v 1 v c mv 1 mv 2 mv 3 (v ss ) v dd v ss v dd v ss c3 cap4 cap4+ c1 + c1 c1 c1 + + + + + cap1+ cap1 cap2 cap2+ v out v dd c1 + + cpp+ cpp cpm+ cpm v 3 v 2 v 1 v c mv 1 mv 2 mv 3 (v ss ) c3 cap4 cap4+ c1 + c1 c1 c1 s1d15e06 series s1d15e06 series + + + + 6.6.3 liquid crystal drive voltage generation circuit voltage v c is boosting in the ic to generate potential v 3 . furthermore, voltages v 3 and v c are converted by resistive divider to produce v 2 , v 1 , mv 1 and mv 2 voltages. v 2 , v 2 , mv 1 and mv 2 voltages are impedance-converted by the voltage follower, and is supplied to the liquid crystal drive circuit. v 2 11/14 v 3 v 1 9/14 v 3 v c 7/14 v 3 mv 1 5/14 v 3 mv 2 3/14 v 3
s1d15e06 series rev. 2.1 epson 25 only v out = v dd is used: (9 c?) 2 v c regulating circuit and lcdv circuit v out external input (10 c?) 3 lcdv circuit only v c external input (9 c?) 4 external power supply only external input (1 c) + + + + cap1+ cap1 cap2 cap2+ v out v dd + cpp+ cpp cpm+ cpm v 3 v 2 v 1 v c mv 1 mv 2 mv 3 (v ss ) v dd v ss v dd v ss c3 cap4 cap4+ c1 + c1 c1 + + + + cap1+ cap1 cap2 cap2+ v out v dd + cpp+ cpp cpm+ cpm v 3 v 2 v 1 v c mv 1 mv 2 mv 3 (v ss ) c3 cap4 cap4+ c1 + c1 c1 v out s1d15e06 series s1d15e06 series + + + + + + + + cap1+ cap1 cap2 cap2+ v out v dd + cpp+ cpp cpm+ cpm v 3 v 2 v 1 v c mv 1 mv 2 mv 3 (v ss ) v dd v ss c3 cap4 cap4+ c1 + c1 c1 s1d15e06 series v c cap1+ cap1 cap2 cap2+ v out v dd + cpp+ cpp cpm+ cpm v 3 v 2 v 1 v c mv 1 mv 2 mv 3 (v ss ) v dd v ss cap3+ cap3 cap4 cap4+ c1 external power supply s1d15e06 series + +
s1d15e06 series 26 epson rev. 2.1 examples of common reference settings item settings unit c1 1.0 to 4.7 the optimum values for above-mentioned cl, c2 and c3 vary according to the lcd panel to drive. use the above-mentioned values as references. actually verify the display of a pattern with big load to make a decision. 6.6.4 temperature gradient select circuit this is a circuit to select the temperature gradient characteristics of the liquid crystal drive power supply voltage. temperature gradient characteristics can be selected from eight states by the temperature gradient command. selection of temperature gradient characteristics conforming to the temperature characteristics of the liquid crystal to be used makes it possible to configure a system without providing an external element for temperature characteristics compensation. 6.7 reset circuit when the res input becomes low, this lsi is set to the initialized state. the following shows the initially set state: 1. display : off 2. display off mode : v ss output 3. display : normal mode 4. display all lighting : off 5. common output status : normal 6. display start line : set to 1st line 7. page address : set to 0 page 8. column address : set to 0 address 9. display data input direction : column direction 10. column address direction : forward 11. n-line a.c. reverse drive : off (reverse drive for each frame) 12. n-line reverse drive register : (d4, d3, d2, d1, d0) = (0, 1, 1, 0, 0) 13. display mode : 4 gray-scale display 14. gray-scale pattern register : (d7, d6, d5, d4, d3, d2, d1, d0) = ( * , 1, 0, 1, * , 0, 1, 0) 15. area scroll : scroll mode : (d1, d0) = (0, 0) scroll start address : (d7, d6, d5, d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0, 0, 0, 0) scroll terminating address : (d7, d6, d5, d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0, 0, 0, 0) number of display lines : (d7, d6, d5, d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0, 0, 0, 0) 16. duty register : (d5, d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0, 0) (1/132 duty) start spot (block) register : (d5, d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0) (com0) 17. partial display : off 18. partial display start line : (d7, d6, d5, d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0, 0, 0) number of partial display lines : (d7, d6, d5, d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0, 0, 0) 19. read modify write : off 20. built-in oscillation circuit : stop 21. oscillation frequency register : (d3, d2, d1,d0) = (0, 0, 0, 0) (120 khz) 22. power control register : (d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0) 23. clock frequency for step-up/step-down step-up : (d2, d1, d0) = (1, 0, 1) step-down : (d6, d5, d4) = (1, 0, 1) 24. liquid crystal drive voltage selection register : (d1,d0) = (0, 0) 25. electronic volume register : (d6, d5, d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0, 0, 0) 26. discharge : on (only for when res = low) 27. power save : off 28. temperature gradient resistor : (d2, d1, d0) = (0, 0, 0) (?.06/ c) 29. register data in the serial interface : clear when the reset command is used, only the above- mentioned inilialized items 7, 8 and 19 are executed. when power is turned on, initialization by the res pin is necessary. after initialization by the res pin, each input pin must be controlled correctly. furthermore, when control signals from the mpu have a high impedance, the excessive current may flow to the ic. after v dd is applied, measures should be taken to ensure that the input pin does not have a high impedance. the s1d15e06 series discharges the electric charge of v out and liquid crystal drive voltage (v 3 , v 2 , v 1 , v c , mv 1 , mv 2 ) at the level of res pin = low. when liquid crystal drive external power supply is used, external power supply should not be supplied during the period of res = low to prevent external power supply and v dd from being short circuited. *5 precautions when installing the cog when installing the cog, it is necessary to duly consider the fact that there exists a resistance of the ito wiring occurring between the driver chip and the externally connected parts (such as capacitors and resistors). by the influence of this resistance, non-conformity may occur with the indications on the liquid crystal display. when installing the cog, we recommend to use the " 4 external power supply only"
s1d15e06 series rev. 2.1 epson 27 7. command the s1d15e06 series identifies data bus signals by a combination of a0, rd(e) and wr(r/w). interpretation and execution of the command are executed by the internal timing alone which is independent of the external clock. this allows high-speed processing. the 80 series mpu interface allows the command to be started by entering the low pulse in the rd pin during reading and by entering the low pulse in the wr pin during writing. the 68 series mpu interface allows a read state to occur by entering high in the r/w pin, and permits a write state to occur by entering low. it also allows the command to be started by entering the high pulse in the pin e. (for timing, see the description of ?0. timing characteristics?. accordingly, the 68 series mpu interface is different from 80 series mpu interface in that rd(e) is ?(h)?in the case of display data/read shown in the command description and command table. the following describes the commands, based on the example of the 80 series mpu interface: when the serial interface is selected, enter data sequentially starting from d7. command description (1) display on/off this command sets the display on/off. when display off is specified, segment and common drivers outputs the level selected by the display off mode select command. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 output level 0 1 0 1 0 1 0 1 1 1 0 display off 1 display on e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 output level 01010111110 v ss 1v c (3) display normal/reverse this command allows the display on/off state to be reversed, without having to rewrite the contents of the display data ram. in this case, contents of the display data ram are maintained. (2) display off mode select this command is used to set the output level of the segment and common driver when the display is off. in the initial setting state, it becomes "d0 = 0". * when d0 = 0 is selected in the case of s1d15e06d00b * , the mv 2 and common driver v ss level is output by segment driver when display is off. select d0 = 1 to use the s1d15e06d00b * . e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 0 1 1 0 ram data = high lcd on voltage (normal) 1 ram data = low lcd on voltage (reverse)
s1d15e06 series 28 epson rev. 2.1 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 selected state 0 1 0 11000100 normal com0 (4) display all lighting on/off this command forces all the displays to be turned on independently of the contents of the display data ram. in this case, the contents of the display data ram are maintained. fully white display can also be made by a combination of the display reverse command. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010100100 normal display status 1 display all lighting (5) common output status select this command allows the scanning direction of the com output pin to be selected. for details, see the description of ?.5.2 com drivers?in the function description. (6) display start line set (parameter: 1 byte (4 gray-scale) and 2 bytes (binary)) the parameter following this command specifies the display start line address of the display data ram shown in fig. 6.5 and 6.6. when the display mode command is used to select 4 gray-scale display, a 1-byte parameter must be entered. when the binary display is selected, a 2-byte parameter must be entered. the display area is indicated in the direction where line address numbers are incremented, starting from the specified line address. if a dynamic change of the line address is made by this command, smooth scrolling in the longitudinal direction and page breaking are enabled. for details, see the description of ?.2.4 line address circuit?in the function description. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 0 1 0 1 0 mode setting 1 1 0 p7 p6 p5 p4 p3 p2 p1 p0 register setting 1 110 ******* p8 register setting 2 (only binary display required) *: denote invalid bits.
s1d15e06 series rev. 2.1 epson 29 line p7 p6 p5 p4 p3 p2 p1 p0 address 00000000 00h 00000001 01h 00000010 02h set to the line address 00h at the time of resetting. ?display start line set command parameter (i) when the display mode is a 4 gray-scale mode: the one-byte parameter is used to specify the address. (ii) when the display mode is binary: to specify the address, continuous 2-byte data is necessary. the first byte d0 is lsb, and the second byte d0 is mlb. 1st byte 2nd byte p7 p6 p5 p4 p3 p2 p1 p0 line p8 address 00000000 00h ******* 0 00000001 01h ******* 0 00000010 02h ******* 0 ******* 1 0 0 0 0 0 1 1 1 107h ******* 1 set to line address 000h at the time of resetting. *: denote invalid bits. fig. 7.1 ?line address setting sequence yes no change completed? set line address register set line address mode reset line address mode one byte for 4 gray-scale two bytes for binary display
s1d15e06 series 30 epson rev. 2.1 (7) page address set this command specifies the page address corresponding to row address when mpu access to the display data ram shown in fig. 6.5 and 6.6. for details, see the description of ?.2.2 page address circuit?in the function description. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 page address 0 1 0 1 0 1 1 0 0 0 1 command 110 ** p5 p4 p3 p2 p1 p0 page address setting *: denote invalid bits. p5 p4 p3 p2 p1 p0 page address 000000 0 000001 1 (8) column address set this command sets the display data ram column address given in fig. 6.5 and 6.6. for details, see the description of ?.2.3 column address circuit?in the function description. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01000010011 1 1 0 p7 p6 p5 p4 p3 p2 p1 p0 column p7 p6 p5 p4 p3 p2 p1 p0 address 00000000 0 00000001 1 00000010 2 (9) display data write this command allows the 8-bit data to be written to the address specified by the display data ram. after writing, column address or page address is automatically incremented +1 by the display data input direction select command. this enables the mpu to write the display data continuously. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01000011101 1 1 0 write data
s1d15e06 series rev. 2.1 epson 31 (10) display data read this command allows the 8-bit data to be read from the address specified by the display data ram. after reading, column address or page address is automatically incremented +1 by the display data input direction select command. this enables the mpu to read multiple word data continuously. it should be noted that one dummy reading is essential immediately after the column address or page address has been set. for details, see the description of ?.1.5 access to display data ram and internal register?in the function description. when the serial interface is used, display data cannot be read. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01000011100 1 0 1 read data (11) display data input direction select this command sets the direction where the display ram address number is automatically incremented. for details, see the description of ?.2.3 column address circuit?in the function description. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 direction 0 1 0 1 0 0 0 0 1 0 0 column 1 page (12) column address set direction this command can reverse the relationship between the display ram data column address and segment driver output shown in fig. 6.5 and 6.6. so you can reverse the sequence of segment driver output pins using this command. when the display data is written or read, the column address is incremented by (+1) according to the column address given in fig. 6.4 and 6.5. for details, see the description of ?.2.3 column address circuit?in the function description. (13) n-line inversion drive register set this command sets the liquid crystal alternating drive reverse line count in the register to start line reverse driving operation. the line count to be set is 4 to 128 (32 states for each 4 lines. for details, see the description of ?.4 display timing generation circuit?in the function description. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010100000 normal 1 reverse e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 reverse line count 0 1 0 0 0 1 1 0 1 1 0 command 110 *** p4 p3 p2 p1 p0 reverse line count *: denote invalid bits. p4 p3 p2 p1 p0 reverse line count 00000 4 (1
s1d15e06 series 32 epson rev. 2.1 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 n-line 01011100100 off 1on (14) n-line on/off this command provides on/off control of n-line inverting drive. (16) gray-scale pattern set this command sets the level of gray-scale. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 gray-scale pattern 0 1 0 0 0 1 1 1 0 0 1 command 110 * p6 p5 p4 * p2 p1 p0 selection of gray-scale level * (p6, p5, p4) : selects the level of gray-scale bit (1, 0) * (p2, p1, p0) : selects the level of gray-scale bit (0, 1) gray-scale bit (1, 0) p6 p5 p4 p2 p1 p0 level of gray-scale 001 white 010 110 black gray-scale bit (0, 1) p6 p5 p4 p2 p1 p0 level of gray-scale 0 0 1 white 010 1 1 0 black (15) display mode this command sets the display mode. 4 gray-scale and binary display each have a different ram configuration. for details, see the description of ?.2.1 display data ram?in the function description. set to 4 gray-scale (d1, d0) = (0, 0) at the time of resetting. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 display mode 0 1 0 0 1 1 0 0 1 1 0 command 110 ****** p1 p0 display mode *: denote invalid bits. p1 p0 display mode 0 0 4gray-scale 0 1 binary value
s1d15e06 series rev. 2.1 epson 33 (17) area scroll set this command sets the area scroll. when the binary display is selected by the display mode set command, the scroll end line address becomes a two-byte parameter. 1 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 area scroll 0 1 0 0 0 0 1 0 0 0 0 command 110 ****** p11 p10 scroll mode 1 1 0 p27 p26 p25 p24 p23 p22 p21 p20 scroll start line address 1 1 0 p37 p36 p35 p34 p33 p32 p31 p30 scroll end line address 1 1 0 p47 p46 p45 p44 p43 p42 p41 p40 scroll display line count *: denote invalid bits. p11 p10 scroll mode 0 0 0 (full screen) 0 1 1 (upper) 1 0 2 (lower) 1 1 3 (central) p27 p26 p25 p24 p23 p22 p21 p20 scroll start line address 00000000 00h 00000001 01h p37 p36 p35 p34 p33 p32 p31 p30 scroll end line address 00000000 00h 00000001 01h p47 p46 p45 p44 p43 p42 p41 p40 scroll display line count 00000001 1 00000010 2
s1d15e06 series 34 epson rev. 2.1 2 binary display e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 area scroll 0 1 0 0 0 0 1 0 0 0 0 command 110 ****** p11 p10 scroll mode 1 1 0 p27 p26 p25 p24 p23 p22 p21 p20 scroll start line address 1 1 0 p37 p36 p35 p34 p33 p32 p31 p30 scroll end line address 110 ******* p38 1 1 0 p47 p46 p45 p44 p43 p42 p41 p40 scroll display line count *: denote invalid bits. specifications on the parameters for scroll mode, scroll start line address and scroll display line count are the same as those on 4 gray-scale display. p37 p36 p35 p34 p33 p32 p31 p30 scroll end line address p38 binary value 00000000 00h ******* 0 00000001 01h ******* 0 ******* 1 0 0 0 0 0 1 1 1 107h ******* 1 1st byte 2nd byte (18) duty set command liquid crystal drive at a lower power consumption is ensured by using this command to change the duty. use of this command also allows display at a desired position on the panel (continuous com pins on a 4-line basis). this command is used with a pair of the duty set parameter and start point (block) parameter, so be sure to set both parameters so that one of them will immediately follow the other. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 selected state 0 1 0 0 1 1 0 1 1 0 1 duty set command 110 ** p15 p14 p13 p12 p11 p10 duty set 110 ** p25 p24 p23 p22 p21 p20 start point set *: denote invalid bits. ?duty set duty can be set in the range from 1/4 duty to 1/132 duty by 4 steps. set to 1/132 duty after resetting. p15 p14 p13 p12 p11 p10 duty set 0 0 0 0 0 0 1/4 duty set 0 0 0 0 0 1 1/8 duty set 0 0 0 0 1 0 1/12 duty set 0 0 0 0 1 1 1/16 duty set
s1d15e06 series rev. 2.1 epson 35 ?start point (block) register set parameter use this parameter to set 6-bit data in the start point (block) register. then one of 33 start point blocks will be determined . * use the display start line set command (6) for display scroll. do not use this command for display scroll. set to 0 block (d7 to d0: ***00000) at the time of resetting * voltage optimum to liquid crystal drive is changed when the duty is changed. use the electronic volume and set the voltage to get the optimum display. ?duty command setup example 1. duty 1/88 when 1 (com4 to com7) is specified as the start point (block) display area com4 to com91 2. duty 1/68 when 26 (com104 to com107) is specified as the start point (block) display area com104 to com131 and com0 to com39 * if the com pin is not shared by the master and slave in the master/slave 2-chip operation (for vertical drive such as seg132, com80+com80), the same duty must be used on the master and slave. otherwise, display contrast will be different on the master and slave. when you want to disable display on either the master and slave, use the display off mode select command to set the side you want to disable, so that v c level is output. (19) partial display on/off the lcd partial display is turned on or off by this command. p25 p24 p23 p22 p21 p20 start piont setting 0 0 0 0 0 0 0 (com0 to 3) 0 0 0 0 0 1 1 (com4 to 7) 0 0 0 0 1 0 2 (com8 to 11) e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 partial display 01010010110 off 1on (20) partial display set this command sets the lcd partial display area. duty is placed in the state selected by the duty set command. when partial display is switched by this command, liquid crystal drive voltage need not be changed. for details, see the description of ?.2.7 partial display?in the function description. p17 p16 p15 p14 p13 p12 p11 p10 display start line 00000000 0 00000001 1 00000010 2 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 partial display 0 1 0 0 0 1 1 0 0 1 0 command 1 1 0 p17 p16 p15 p14 p13 p12 p11 p10 display start line 1 1 0 p27 p26 p25 p24 p23 p22 p21 p20 display line count
s1d15e06 series 36 epson rev. 2.1 * the result of display start line added to display line count exceeding 132 should be disregarded. (21) read modify write this command is paired with end command for use. if this command is entered, the column address is not changed by the display data read command. it can be incremented +1 by the display data read command alone. this state s retained until the end command is input. if the end command is input, the column address goes back to the address when the read modify write command is input. this function reduces the mpu loads when changing the data repeated in the specific display area such as blinking cursor. * a command other than display data read/write command can be used in the read modify write mode. however, you cannot use the column address set command. ?sequence for cursor display p17 p16 p15 p14 p13 p12 p11 p10 display start line 00000001 1 00000010 2 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100000 fig. 7.2 page address set column address set dummy read data read data write end yes no change completed? read modify write data manipulation
s1d15e06 series rev. 2.1 epson 37 (22) end this command releases the read modify write mode and gets column address back to the initial address of the mode. fig. 7.3 (23) built-in oscillator circuit on/off this command starts the built-in oscillator circuit operation. it is enabled only in the master operation mode (m/s = high) when built-in oscillator circuit is valid (cls = high). when the built-in power supply is used, the oscillator circuit on command must be executed before the power control set command. (see the description of ?16) power control command?. if the built-in oscillator circuit is turned off when the built-in power supply is used, display failure may occur. e r/w built-in oscillator a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 circuit 01010101010 off 1on e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011101110 n n+m n+3 n+2 n+1 n column address set read-modify-write mode end return
s1d15e06 series 38 epson rev. 2.1 (24) built-in oscillator circuit frequency select this command sets the built-in oscillator circuit frequency. the frequency can be selected whether the built-in oscillator circuit is turned on or off. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 f osc khz f cl khz 0 1 0 0 1 0 1 1 1 1 1 command command 110 **** p3 p2 p1 p0 oscillation cl frequency frequency oscillation cl frequency frequency f cl khz p3 p2 p1 p0 f osc khz 0 0 0 0 120.0 f osc 120.0 0 0 0 1 100.0 f osc 100.0 0010 88.0 f osc 88.0 0011 76.0 f osc 76.0 0 1 0 0 120.0 f osc /2 = 60.0 0 1 0 1 100.0 f osc /2 = 50.0 0110 88.0f osc /2 = 44.0 0111 76.0f osc /2 = 38.0 1 0 0 0 120.0 f osc /4 = 30.0 1 0 0 1 100.0 f osc /4 = 25.0 1010 88.0f osc /4 = 22.0 1011 76.0f osc /4 = 19.0 1 1 0 0 120.0 f osc /8 = 15.0 1 1 0 1 100.0 f osc /8 = 12.5 1110 88.0f osc /8 = 11.0 1111 76.0f osc /8 = 9.5 (d7 to d0: ****0000) is set after resetting. * the above-mentioned value is a typ. value at 25 c. there is a tolerance of 12% at 25 c.
s1d15e06 series rev. 2.1 epson 39 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 selected state 0 1 0 0 0 1 0 0 1 0 1 command 1 1 0 0 0 0 p4 p3 p2 p1 p0 register set (25) power control set this command sets the built-in power supply circuit function. for details, see the description of ?.7 power supply circuit?in the function description. p4 p3 p2 p1 p0 selected state 1 1 triple step-up 1 0 double step-up 01 v out = v dd 0 step-up: off 1 step-up: on 0v c : off 1v c : on 0 lcd voltage: off 1 lcd voltage: on s1d15e06d00b * : (lcd voltage: v 2 , v 1 , mv 1 ) s1d15e06d00b * : (lcd voltage: v 3 , v 2 , v 1 , mv 1 , mv 2 ) an internal clock is required to operate the built-in power supply circuit. during the operation of the built-in power supply circuit, be sure that the internal clock is present inside. if the built-in oscillator circuit is used, execute the built-in oscillator circuit on command before the power control set command. if an external oscillator circuit is used, operate the external oscillator circuit before the power control set command. if the internal clock is cut off during the operation of the built-in power supply circuit, display failure may occur. to avoid this, do not cut it off. in the slave operation mode, only the parameters (d7 to d0 : ***00000) can be used with the power control set command. do not use any other parameter. 100ms or more should be kept from v c regulator circuit on to lcdv circuit on. fig. 7.4 power control set 1. step-up circuit on 2. v c regulator circuit on 3. lcdv circuit on * built-in oscillator on external oscillator input a built-in oscillator used an external oscillator used
s1d15e06 series 40 epson rev. 2.1 (26) step-up ck frequency select this command selects the step-up ck and step-down ck frequencies. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 1 0 0 0 0 0 1 command 110 * p6 p5 p4 * p2 p1 p0 register *: denote invalid bits. (fosc/32) is set after resetting. step-up ck p6 p5 p4 p2 p1 p0 step-up ck 011 f osc /8 100 f osc /16 101 f osc /32 111 f osc /128 it should not use the following. (p2, p1, p0) = (0, 0, 0) , (0, 0, 1) , (0, 1, 0) step-down ck * p6 p5 p4 * 000 p2 p1 p0 step-down ck 011 f osc /8 100 f osc /16 101 f osc /32 110 111 f osc /128 it should not use the following. (p6, p5, p4) = (0, 0, 0) , (0, 0, 1) , (0, 1, 0) * for s1d15e06d00b * , the step-down ck register is disabled. (27) liquid crystal drive voltage select the liquid crystal drive voltage range issued from the liquid crystal drive voltage regulating circuit is selected from 3 states by this command. e r/w v c voltage a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 output range 0 1 0 0 0 1 0 1 0 1 1 command 110 ****** p1 p0 register *: denote invalid bits. v c voltage p1 p0 output range 0 0 1.77 to 3.50 v 1 0 2.53 to 5.00 v 1 1 3.54 to 7.00 v v c voltage output range, 1.77 to 3.50v, (d1, d0) = (0, 0) is set after resetting.
s1d15e06 series rev. 2.1 epson 41 (28) electronic volume this command controls liquid crystal drive voltage v c issued from the built-in liquid crystal power supply voltage regulating circuit, and adjusts the liquid crystal display density. for details, see the description of 6.6.2 voltage regulating circuit in the function description. ?electronic volume register set when a 7-bit data to the electronic volume register is set by this command, liquid crystal drive voltage v c assumes one state out of voltage values in 128 states. after this command is input, and the electronic volume register is set, the electronic volume mode is reset. ?electronic volume register set sequence e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 0 0 0 0 1 command 110 * p6 p5 p4 p3 p2 p1 p0 register *: denote invalid bits. fig. 7.5 p6 p5 p4 p3 p2 p1 p0 v c 0 0 0 0 0 0 0 smaller 0000001 0000010
s1d15e06 series 42 epson rev. 2.1 (29) discharge on/off this command discharges the capacitors connected to the power supply circuit. this command is used when the system power of this ic (s1d15e06 series) is turned off, and the duty is changed. see the description of (3) power supply off and (4) changing the duty in the instruction setup: reference. * if this command is executed when the external power supply is used, a large current may flow to damage the ic. if external power supply is used to drive liquid crystal, be sure to turn off the external power supply before executing this command. (30) power saving this command establishes the power save mode, thereby ensuring a substantial reduction of current consumption. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 1 1 0 1 0 1 0 discharge off 1 discharge on in the power save mode, display data and operation before power saving are maintained. access to the display data ram from the mpu is also possible. the current consumption is reduced to the value close to static current if all operations of the lcd display system are stopped and there is no access from the mpu. in the power save mode, the following occurs: stop of oscillator circuit stop of lcd power supply circuit stop of all liquid crystal drive circuit (v ss level output is issued as the segment and common driver output). the power save off command releases the power save mode. the system goes back to the state before the power save mode. * when the external power supply is used, it is recommended to stop the external power supply circuit function when the power save mode is started. for example, when each level of the liquid crystal drive voltage is given from the external resistive divider circuit, it is recommended to add a circuit to cut off the current flowing to the resistive divider circuit when power save function is started. the s1d15e06 series has a liquid crystal display blanking control control pin dof, and the level goes low when power save function is started. you can use the dof output to stop the external power supply circuit function. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 power save mode 01010101000 off 1on
s1d15e06 series rev. 2.1 epson 43 (31) temperature gradient set the 3-bit data of this command is used to set the temperature gradient characteristics of the liquid crystal drive voltage output from the built-in power supply circuit from eight states to one state. the temperature gradient of the liquid crystal drive voltage can be set according to the liquid crystal temperature gradient to be used. this eliminates the need of a temperature characteristics regulating circuit to be installed outside this ic (s1d15e06 series). e r/w temperature a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 gradient [%/ c] 0 1 0 0 1 0 0 1 1 1 0 command 110 ***** p2 p1 p0 register *: denote invalid bits. (32) status read this command reads out the temperature gradient select bit set on the register. temperature p2 p1 p0 gradient [%/ c] 000 0.06 001 0.08 010 0.10 011 0.11 100 0.13 101 0.15 110 0.17 111 0.18 (d7 to d0: *****000) is set after resetting. *: denote invalid bits. e r/w temperature a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 gradient [%/ c] 0 1 0 1 0 0 0 1 1 1 0 command 101 ***** p2 p1 p0 register *: denote invalid bits. temperature p2 p1 p0 gradient [%/ c] 000 0.06 100 0.08 010 0.10 110 0.11 001 0.13 101 0.15 011 0.17 111 0.18
s1d15e06 series 44 epson rev. 2.1 (33) reset this command resets the column address, page address, read modify write mode and test mode without giving adverse effect to the display data ram. for details, see the description of 6.8 reset in function description. resetting is carried out after the reset command has been input. initialization upon application of power supply is carried out by the reset signal to the res pin. the reset command cannot be used for this purpose. (34) mls drive selection command these are the mls drive selection commands. these commands changes over between the dispersive drive and nondispersive drive. * indicates the invalid bits. after resetting, nondispersive drive will be preset in 4 gradation indications. in case the b/w indication is selected after resetting, dispersive drive will be preset. dispersive drive and nondispersive drive are the lcd drive methods characteristic to the mls drive. the s1d15e06 series is making 4 line mls drive and, 4 times higher period selection voltage than that of the period being used for indication of 1 line in an ordinary drive (in case of 132 line indication, the period of 1/132 of 1 frame). in case of the dispersive drive, the selection signals will be output for four times, separately, within the period of 1 frame. with this dispersive drive method, it is possible to reduce the frame frequency as compared with the nondispersive drive method. therefore, when it becomes necessary to reduce the current consumption, we recommend you to use this dive method. however, in case of the drive method where moving pictures are to be indicated, the indication may become flickered and this dispersive drive method is not suitable for indications of moving pictures. (35) nop this is a non-operation command. note: s1d15e06 series maintains the operation status due to the command. however, when exposed to excessive external noise, internal status may be changed. this makes it necessary to take some measures which reduces noise generation in terms of installation or system configuration, or which protects the system against adverse effect of noise. to cope with sudden noise, it is recommended to refresh the operation status on a periodic basis. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100010 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100011 e r/w temperature gradient a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 [%/?c] 01010011100 command 110 **** p3 p2 p1 p0 register temperature gradient p3 p2 p1 p0 [%/?c] 0000 dispersive drive 1000 nondispersive drive
s1d15e06 series rev. 2.1 epson 45 command code command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function (1) display on/off 0 1 0 1 0 1 0 1 1 1 0 lcd display on/off control. 1 0: off, 1: on (2) display off mode 0 1 0 1 0 1 1 1 1 1 0 output level when the display is off and in select 1 the power save mode 0: v ss , 1: v c (3) display normal 0 1 0 1 0 1 0 0 1 1 0 lcd display normal/reverse /reverse 1 0: normal, 1: reverse (4) display all lighting 0 1 0 1 0 1 0 0 1 0 0 display all lighting on/off 1 0: normal display, 1: all on (5) common output 0 1 0 1 1 0 0 0 1 0 0 selects com output scan direction. status select 1 0: normal, 1: reverse (6) display start line set 0 1 0 1 0 0 0 1 0 1 0 sets display start line. 1 1 0 display start line address when the display mode is binary, 11 0 * ****** table 7.1 table of commands in s1d15e06 series
s1d15e06 series 46 epson rev. 2.1 command code command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function (26) step-up ck 0 1 0 0 1 0 0 0 0 0 1 frequency select 1 1 0 * frequency (27) liquid crystal drive 0 1 0 0 0 1 0 1 0 1 1 voltage select 1 1 0 ****** v c range (28) electronic volume 0 1 0 1 0 0 0 0 0 0 1 mode set electronic volume 1 1 0 * electronic volume v c output voltage is set to the register set electronic volume register. 128 states (29) discharge on/off 0 1 0 1 1 1 0 1 0 1 0 discharges power supply circuit 1 connection capacitor. 0: off (normal), 1: on (30) power save on/off 0 1 0 1 0 1 0 1 0 0 0 power save 0: off, 1: on (31) temperature 0 1 0 0 1 0 0 1 1 1 0 sets to 8 steps. gradient select 1 1 0 ***** temperature gradient (32) stator read 0 1 0 1 0 0 0 1 1 1 0 issues the temperature gradient 10 1 ***** temperature gradient select bit. (33) reset 0 1 0 1 1 1 0 0 0 1 0 resets the column, page and address registers.resets the read modify write function. (34) mls drive selection 0 1 0 1 0 0 1 1 1 0 0 mls drive method 11 0 **** mls drive method 0 : dispersive, 1 : nondispersive (35) nop 0 1 0 1 1 1 0 0 0 1 1 non-operation command
s1d15e06 series rev. 2.1 epson 47 stable power supply * 1 v dd - v ss power turns on when res terminal = low. release the reset state. (res terminal = high) function setup by command entry (set by users) (12) column address set direction (5) common output status select (3) display normal/reverse (4) display all lighting on/off (18) set the duty (2) display off mode select (27) lcd voltage select (28) electronic volume (31) temperature gradient set initialization completed function setup by command entry (set by users) (13) n-line invert drive register set (14) n-line on/off function setup by command entry (set by users) (24) built-in oscillator circuit frequency select (23) built-in oscillator circuit on/off function setup by command entry (set by users) (25) power control set 1. step-up circuit on 2. v c regulator circuit on 3. lcdv circuit on * 2 (when the n-line invert drive is not used) (when the external oscillator circuit is used) (when the external lcd power supply circuit is used) enter the external clock external lcd power supply entry instruction setup example (reference) (1) initial setup note: *1 display data ram contents are not determined even in the initialized state after resetting. see 6.7 reset circuit in the 6. function description . *2 100ms or more should be kept from v c regulator circuit on to lcdv circuit on. * numerals in the command parenthesis correspond to the numerals of the items in command description.
s1d15e06 series 48 epson rev. 2.1 end of initialization end of data display function setup by command entry (set by users) (6) display start line set (7) page address set (8) column address set function setup by command entry (set by users) (9) display data write function setup by command entry (set by users) (1) display on/off command a desired state v dd - v ss power supply off function setup by command entry (set by users) (30) power save on function setup by command entry (set by users) (29) discharge on/off external lcd power supply off (when an external lcd power supply circuit is used) reset state (res terminal = low) (when the built-in power supply circuit is used) set the time (t l ) between entry into the reset state and turning off of v dd -v ss power supply liquid crystal drive potential (mv 1 ,v c ,v 1 ,v 2 ) so that it is longer than the time (t h ) where it is reduced below the threshold value of the lcd panel. (2) data display note: * display data ram contents are not determined after end of initialization. write data to all the display data ram used for display. see 9. display data write in the 7. command description . (3) power off note: * this ic controls the circuit of the liquid crystal drive power supply system using the v dd -v ss power supply circuit. if the v dd -v ss power supply is cut off with voltage remaining in the liquid crystal drive power supply system, voltage not controlled will be issued from the seg and com pins, and this may result in display failure. to avoid this, follow the above-mentioned power off sequence.
s1d15e06 series rev. 2.1 epson 49 function setup by command entry (set by users) (28) electronic volume (24) built-in oscillator circuit frequency select (18) duty set when the n-line reversing command is used : (13) n-line reverse drive register set function setup by command entry (set by users) (1) displya off function setup by command entry (set by users) (30) power save on function setup by command entry (set by users) (29) discharge on function setup by command entry (set by users) (29) discharge off function setup by command entry (set by users) (30) power save off a desired state end of duty change secure an interval of 30ms or more between discharge on to discharge off . note: * execution of the above sequence causes display to be turned off temporarily (for the time from power saving command on to power saving command off plus 200 ms (frame frequency 60hz) upon switching of the duty. temporary display failure may occur if duty change command is executed during liquid crystal display without executing the above-mentioned setup example. follow the setup example when the duty is changed as discussed above. (5) refresh it is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected noise. (4) how to change the duty set all commands to the ready state (including default state setting.) nop command refresh sequence refreshing of dram
s1d15e06 series 50 epson rev. 2.1 item symbol specified value unit power voltage (1) v dd 0.3 to +4.0 v power voltage (2) v 3 , v out 0.3 to +17.0 power voltage (3) v 2 , v 1 , v c , mv 1 , mv 2 0.3 to v 3 input voltage v in 0.3 to v dd +0.3 output voltage v o 0.3 to v dd +0.3 operating temperature t opr 40 to +85 55 to +100 bare chip 55 to +125 system (mpu) side v cc gnd v 2 , v 1 ,mv 1 ,mv 2 v dd v out v c v 3 v ss s1d15e06 side table 8 v ss = 0v unless otherwise specified. fig. 8 notes: 1. v oltages v 3 , v 2 , v 1 , v c , mv 1 , mv 2 and mv 3 (v ss ) must always meet the conditions of v 3 8. absolute maximum ratings
s1d15e06 series rev. 2.1 epson 51 table 9.1 9. dc characteristics v ss = 0v, v dd = 2.7v 40 to +85 specified value applicable item symbol conditions min. typ. max. unit pin working voltage (1) operation enabled v dd 1.7 3.6 v v dd * 1 working voltage (2) operation recommended v out v dd 16.0 v out working voltage (3) operation enabled v 3 applicable to 3.4 14.0 v 3 * 2 operation enabled v c s1d15e06d01 **** 1.7 7.0 v c operation enabled v 2 v c v 3 v 2 operation enabled v 1 v c v 3 v 1 operation enabled mv 1 v ss v c mv 1 operation enabled mv 2 v ss v c mv 2 working voltage (4) operation enabled v 3 applicable to 3.4 16.0 v 3 * 2 operation enabled v c s1d15e06d03 **** 1.7 8.0 v c operation enabled v 2 v c v 3 v 2 operation enabled v 1 v c v 3 v 1 operation enabled mv 1 v ss v c mv 1 operation enabled mv 2 v ss v c mv 2 high-level input voltage v ihc v dd =1.7v to 3.6v 0.8 v dd * 3 low-level input voltage v ilc v ss 0.2 0.25ma 0.8 v dd * 4 low-level output voltage v olc to 3.6v i ol =0.25ma v ss 0.2 1.0 1.0 3.0 3.0 * 6 lcd driver on resistance r on ta=25 1.5 2.3 k ? 3.0 4.6 comn * 7 static current consumption i ddq ta=25 0.2 5.0 1.0 5.0 v 3 input pin capacity c in ta=25 20 25 pf oscillation built-in oscillation f osc ta=25
s1d15e06 series 52 epson rev. 2.1 display mode in 4 gray-scale at f fr = 80hz table 9.4 display: heavy load display code: i ss (1) display mode in binary at f fr = 60hz table 9.5 display entirely in white code: iss (1) v dd boosting v 3 voltage 1/132 duty 1/100 duty unit remarks typ. max. typ. max. 2.7v triple 10v 241 400 187 310 v dd boosting v 3 voltage 1/132 duty 1/100 duty unit remarks typ. max. typ. max. 2.7v triple 10v 65 108 50 83 table 9.2 specified value applicable item symbol conditions min. typ. max. unit pin input voltage v dd double boosting 1.7 3.6 v v dd v dd triple boosting 1.7 3.6 boosted output voltage (1) v out s1d15e06d01 **** 14.0 v out boosted output voltage (2) v out s1d15e06d03 **** 16.0 v out working voltage for voltage v c 1.8 8.0 v c * 9 control circuit built-in power circuit dynamic current consumption (1): built-in power is turned on during display. ta=25 display mode in 4 gray-scale at f fr = 80hz table 9.3 display entirely in white code: i ss (1) v dd boosting v 3 voltage 1/132 duty 1/100 duty unit remarks typ. max. typ. max. 2.7v triple 10v 68 112 67 111
s1d15e06 series rev. 2.1 epson 53 table 9.7 item symbol condition specified value unit remarks min. typ. max. sleep state i dds1 0.2 5 display mode in binary at f fr = 60hz table 9.6 display heavy load display code: iss (1) v dd boosting v 3 voltage 1/132 duty 1/100 duty unit remarks typ. max. typ. max. 2.7v triple 10v 188 312 135 224
s1d15e06 series 54 epson rev. 2.1 [reference data 2] dynamic current consumption (2) during lcd display when internal power is used conditions: v dd = 2.7v built-in power supply on triple boosting f fr = 80hz display mode : 4 gray-scale indication pattern : totally white / checker ta = 25 500 250 0 16 32 64 132 1/duty i ss (2) [a] checker v 3 = 12v v 3 = 10v v 3 = 10v v 3 = 12v totally white fig. 9.2 [* see the description on p.57.] [reference data 1] conditions: built-in power supply on 1/132duty f fr = 80hz triple boosting display mode : 4 gray-scale indication pattern: totally white / checker ta = 25 dynamic current consumption (1) during lcd display when internal power is used fig. 9.1 500 250 0 012 34 3.6 1.8 v dd [v] i ss (1) [a] checker v 3 = 12v v 3 = 10v v 3 = 12v v 3 = 10v totally white
s1d15e06 series rev. 2.1 epson 55 [reference data 3] dynamic current consumption (3) during access indicates the current consumption when the checker pattern is always written by f cyc . when not accessed, only i ss (1) remains. conditions: built-in voltage used triple boosting v 3 = 12.0v, v dd = 2.7v ta = 25
s1d15e06 series 56 epson rev. 2.1 [reference data 4] remarks: * 2 operating voltage range (s1d15e06d01 **** ) remarks: * 2 16.0 14.0 0 01234 v dd [v] 3.4 1.7 3.6 v 3 [v] operating range 14.0 10.5 7.0 3.5 0 01234 v dd [v] 3.4 1.7 3.6 v 3 [v] operating range fig. 9.4.1 operating voltage range (s1d15e06d03 **** ) fig. 9.4.2 [* see the description on p.57.]
s1d15e06 series rev. 2.1 epson 57 ( f fr indicates the cycle of rewriting one screen; it does not indicate fr signal cycle.) [asterisked references] *1. does not guarantee if there is an abrupt voltage variation during mpu access. *2. for v dd and v 3 system operating voltage range, see fig. 9.5. applicable when the external power supply is used. *3. a0, d0 to d5, d6(scl), d7(si), rd(e), wr(r/w), cs1, cs2, cls, cl, fr, f1, f2, ca, m/s, c86, p/s, dof, res and test pins *4. d0 to d7, fr, dof, cl, f1, f2 and ca pins *5. a0, rd(e), wr(r/w), cs1, cs2, cls, m/s, c86, p/s, res and test pins *6. applicable when d0 to d5, d6(scl), d7(s1), cl, fr, dof, f1, f2 and ca pins have a high impedance. *7. indicates the resistance when 0.1v voltage is applied between the output pin segn or comn and each power supply (v 2 , v 1 , v c , mv 1 , mv 2 ). r on =0.1v/ ? ? relationship between oscillation frequency f osc , display clock frequency f cl and liquid crystal frame f fr table 9.8 item f cl display mode f fr built-in oscillator see p. 24 binary display (f cl
s1d15e06 series 58 epson rev. 2.1 10. timing characteristics (1) system path read/write characteristics 1 (80 system mpu) fig. 10.1 table 10.1.1 a0 cs1 (cs2= 1 ) wr, rd t acc8 t oh8 t ds8 t f t r t cyc8 t ah8 t aw8 t cclr , t cclw t cchr , t cchw t dh8 cs1 (cs2= 1 ) wr, rd * 1 * 2 d0 to d7 (write) d0 to d7 (read) parameter signal symbol condition specified value unit min. max. address hold time a0 t ah8 0 ns address setup time t aw8 0 system write cycle time wr t wcyc8 200 system read cycle time rd t rcyc8 300 control low-pulse width (write) wr t cclw 60 control low-pulse width (read) rd t cclr 100 control high-pulse width (write) wr t cchw 60 control high-pulse width (read) rd t cchr 100 data setup time d0 to d7 t ds8 20 data hold time t dh8 10 rd access time t acc8 c l =100pf 80 output disable time t oh8 10 80 [v dd = 3.0v to 3.6v, ta = 40 to +85
s1d15e06 series rev. 2.1 epson 59 table 10.1.2 table 10.1.3 parameter signal symbol condition specified value unit min. max. address hold time a0 t ah8 0 ns address setup time t aw8 0 system write cycle time wr t wcyc8 400 system read cycle time rd t rcyc8 600 control low-pulse width (write) wr t cclw 100 control low-pulse width (read) rd t cclr 250 control high-pulse width (write) wr t cchw 140 control high-pulse width (read) rd t cchr 250 data setup time d0 to d7 t ds8 40 data hold time t dh8 20 rd access time t acc8 c l =100pf 200 output disable time t oh8 10 200 [v dd = 1.7v to 2.4v, ta = 40 to +85 parameter signal symbol condition specified value unit min. max. address hold time a0 t ah8 0 ns address setup time t aw8 0 system write cycle time wr t wcyc8 300 system read cycle time rd t rcyc8 400 control low-pulse width (write) wr t cclw 80 control low-pulse width (read) rd t cclr 200 control high-pulse width (write) wr t cchw 80 control high-pulse width (read) rd t cchr 200 data setup time d0 to d7 t ds8 30 data hold time t dh8 15 rd access time t acc8 c l =100pf 120 output disable time t oh8 10 120 [v dd = 2.4v to 3.0v, ta = 40 to +85 t cclw t cchw ) or ( t r + t f) t cclr t cchr ). *4. timing is entirely specified with reference to 20% or 80% of v dd . *5. t cclw and t cclr are specified in terms of the overlapped period when cs1 is at low (cs2 = high) level and wr and rd are at low level.
s1d15e06 series 60 epson rev. 2.1 (2) system path read/write characteristics 2 (68 system mpu) fig. 10.2 table 10.2.1 [v dd = 3.0v to 3.6v, ta = 40 to +85 1 ) e d0 to d7 (write) d0 to d7 (read) t acc6 t oh6 t ds6 t cyc6 t ah6 t aw6 t ewhr , t ewhw t f t r t ewlr , t ewlw t dh6 cs1 (cs2= 1 ) e * 1 * 2 parameter signal symbol condition specified value unit min. max. address hold time a0 t ah6 0 ns address setup time t aw6 0 system write cycle time e t wcyc6 200 system read cycle time t rcyc6 300 data setup time d0 to d7 t ds6 20 data hold time t dh6 10 access time t acc6 c l =100pf 80 output disable time t oh6 10 80 enable high-pulse width read e t ewhr 100 write t ewhw 60 enable low-pulse width read e t ewlr 100 write t ewlw 60
s1d15e06 series rev. 2.1 epson 61 parameter signal symbol condition specified value unit min. max. address hold time a0 t ah6 0 ns address setup time t aw6 0 system write cycle time e t wcyc6 300 system read cycle time t rcyc6 400 data setup time d0 to d7 t ds6 30 data hold time t dh6 15 access time t acc6 c l =100pf 120 output disable time t oh6 10 120 enable high-pulse width read e t ewhr 150 write t ewhw 80 enable low-pulse width read e t ewlr 150 write t ewlw 80 table 10.2.2 [v dd = 2.4v to 3.0v, ta = 40 to +85 table 10.2.3 parameter signal symbol condition specified value unit min. max. address hold time a0 t ah6 0 ns address setup time t aw6 0 system write cycle time e t wcyc6 400 system read cycle time t rcyc6 600 data setup time d0 to d7 t ds6 40 data hold time t dh6 20 access time t acc6 c l =100pf 200 output disable time t oh6 10 200 enable high-pulse width read e t ewhr 250 write t ewhw 100 enable low-pulse width read e t ewlr 250 write t ewlw 140 [v dd = 1.7v to 2.4v, ta = 40 to +85 v dd . *5 t ewlw , t ewlr should be set to the overlapping zone where the cs1 is on the low level (cs2 = high level) and where the e is on the high level.
s1d15e06 series 62 epson rev. 2.1 parameter signal symbol condition specified value unit min. max. serial clock period scl t scyc 100 ns scl high pulse width t shw 40 scl low pulse width t slw 40 address setup time a0 t sas 80 address hold time t sah 80 data setup time si t sds 20 data hold time t sdh 20 cs-scl time cs t css 80 t csh 150 [v dd = 3.0v to 3.6v, ta = 40 to +85 1 ) a0 scl si t css t sas t sah t scyc t slw t shw tr tf t sds t sdh t csh (3) serial interface figure 10.3 table 10.3.1
s1d15e06 series rev. 2.1 epson 63 parameter signal symbol condition specified value unit min. max. serial clock period scl t scyc 125 ns scl high pulse width t shw 50 scl low pulse width t slw 50 address setup time a0 t sas 100 address hold time t sah 100 data setup time si t sds 30 data hold time t sdh 30 cs-scl time cs t css 100 t csh 200 [v dd = 2.4v to 3.0v, ta = 40 to +85 parameter signal symbol condition specified value unit min. max. serial clock period scl t scyc 154 ns scl high pulse width t shw 60 scl low pulse width t slw 60 address setup time a0 t sas 120 address hold time t sah 140 data setup time si t sds 40 data hold time t sdh 40 cs-scl time cs t css 120 t csh 350 [v dd = 1.7v to 2.4v, ta = 40 to +85 table 10.3.2 table 10.3.3
s1d15e06 series 64 epson rev. 2.1 cl (out) fr f1, f2 ca t dfr t df1 , f2 t dca parameter signal symbol condition specified value unit min. typ. max. fr delay time fr t dfr c l = 50pf 125 312 ns f1, f2 delay time f1, f2 t df1 , t f2 125 312 ns ca delay time ca t dca 125 312 ns [v dd = 3.0v to 3.6v, ta = 40 to +85 parameter signal symbol condition specified value unit min. typ. max. fr delay time fr t dfr c l = 50pf 150 360 ns f1, f2 delay time f1, f2 t df1 , t f2 150 360 ns ca delay time ca t dca 150 360 ns [v dd = 2.4v to 3.0v, ta = 40 to +85 parameter signal symbol condition specified value unit min. typ. max. fr delay time fr t dfr c l = 50pf 225 514 ns f1, f2 delay time f1, f2 t df1 , t f2 225 514 ns ca delay time ca t dca 225 514 ns [v dd = 1.7v to 2.4v, ta = 40 to +85 table 10.4.1 table 10.4.2 table 10.4.3 *1. valid only in master operation *2. timing is entirely specified with reference to 20% or 80% of v dd .
s1d15e06 series rev. 2.1 epson 65 t rw t r end of resetting during resetting res internal state parameter signal symbol condition specified value unit min. typ. max. reset time t r 0.5 [v dd = 3.0v to 3.6v, ta = 40 to +85 parameter signal symbol condition specified value unit min. typ. max. reset time t r 1.0 [v dd = 2.4v to 3.0v, ta = 40 to +85 parameter signal symbol condition specified value unit min. typ. max. reset time t r 1.5 [v dd = 1.7v to 2.4v, ta = 40 to +85 table 10.5.1 table 10.5.2 table 10.5.3
s1d15e06 series 66 epson rev. 2.1 v dd v cc gnd decoder reset mpu a0 d0 to d7 rd wr res cs1 cs2 a0 d0 to d7 rd wr res a1 to a7 iorq v dd c86 p/s v ss v ss s1d15e06 series v dd v cc gnd decoder reset mpu a0 d0 to d7 e r/w res cs1 cs2 a0 d0 to d7 e r/w res a1 to a15 vma v dd c86 p/s v ss v ss s1d15e06 series v dd v cc gnd decoder reset mpu a0 si scl res cs1 cs2 a0 port 1 port 2 res a1 to a7 v dd or v ss c86 p/s v ss v ss v dd s1d15e06 series 11. mpu interface (reference example) the s1d15e06 series can be connected to the 80 series mpu and 68 series mpu. use of a serial interface allows operation with a smaller number of signal lines. you can expand the display area using the s1d15e06 series as a multi-chip. in this case, the ic to be accesses can be selected individually by the chip select signal. after initialization by the res pin, each input terminal of the s1d15e06 series must be placed under normal control. (1) 80 series mpu fig. 11.1 (2) 68 series mpu fig. 11.2 (3) serial interface fig. 11.3
s1d15e06 series rev. 2.1 epson 67 cl fr dof f1 f2 ca m/s s1d15e06 (master) s1d15e06 (slave) v dd v dd v ss cls cls m/s v 3 v 2 v 1 v c mv 1 mv 2 (v ss ) mv 3 cl fr dof f1 f2 ca v 3 v 2 v 1 v c mv 1 mv 2 mv 3 (v ss ) 12. connection between lcd drivers (reference example) you can easily expand the liquid crystal display area using the s1d15e06 series as a multi-chip. in this case, use the same model as the master and slave systems. fig. 12 master/slave connection example (s1d15e06)
s1d15e06 series 68 epson rev. 2.1 13. lcd panel wiring (reference example) you can easily expand the liquid crystal display area using the s1d15e06 series as a multi-chip. in the case of multi- chip configuration, use the same models. (1) single chip configuration example fig. 13.1 single chip configuration example (s1d15e06) (2) double chip configuration example fig. 13.2 double chip configuration example (s1d15e06) 160 x 132 dots com seg com s1d15e06 master 320 x 132 dots com com seg seg s1d15e06 master s1d15e06 slave
s1d15e06 series rev. 2.1 epson 69 14. s1d15e06t00a *** tcp pin layout note: this does not specify the tcp outside shape. v ss fr cl dof f1 f2 ca test cs1 res a0 wr, r/w rd, e cs2 m/s cls c86 p/s d0 d1 d2 d3 d4 d5 d6, scl d7, si v ss v dd v out cap1+ cap1 cap2 cap2+ cap3+ cap3 cap4 cap4+ v 3 v 2 v 1 v c mv 1 mv 2 (v ss )mv 3 cpp+ cpp cpm+ cpm com131 com130 com129 com128 com 67 com 66 seg 159 seg 158 seg 1 seg 0 com 0 com 1 com 2 com 3 com 64 com 65 chip top view reference
s1d15e06 series 70 epson rev. 2.1 15. tcp dimensions (reference example)
s1d15e06 series rev. 2.1 epson 71 16. cautions cautions must be exercised on the following points when using this development specification: 1. this development specification is subject to change for engineering improvement. 2. this development specification does not guarantee execution of the industrial proprietary rights or other rights, or grant a license. examples of applications described in this development specification are intended for your understanding of the product. we are not responsible for any circuit problem or the like arising from the use of them. 3. reproduction or copy of any part or whole of this development specification without permission of our company, or use thereof for other business purposes is strictly prohibited. for the use of the semi-conductor,cautions must be exercised on the following points: [cautions against light] the semiconductor will be subject to changes in characteristics when light is applied. if this ic is exposed to light, operation error may occur. to protect the ic against light, the following points should be noted regarding the substrate or product where this ic is mounted: (1) designing and mounting must be provided to get a structure which ensures a sufficient resistance of the ic to light in practical use. (2) in the inspection process, environmental configuration must be provided to ensure a sufficient resistance of the ic to light. (3) means must be taken to ensure resistance to light on all the surfaces, backs and sides of the ic

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